As circuitry density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One recent technique finding greater application in achieving reduced transistor size is to form field effect transistors with thin films, which are commonly referred to as "thin film transistor" (TFT) technology.
With thin film transistors, a substantially constant thickness film of material (typically polysilicon) is first provided. A central channel region of the thin film is masked while opposing adjacent source/drain regions are doped with appropriate P or N type conductivity enhancing impurities. A gate insulator and gate is provided either above or below the thin film channel region, thus providing a field effect transistor having active and channel regions formed entirely within a thin film as opposed to a bulk substrate. In the manufacturing of thin film transistors, field implants are provided beneath field oxide regions and are normally of the same conductivity type as the bulk/well type of the substrate for providing greater dopant concentration between the thin film transistors. This provides greater electrical isolation between adjacent transistors. Such higher dopant and implant regions are designed to be positioned immediately beneath the isolation field oxide regions. In the construction of these thin field transistors, such implants are normally immediately provided after field oxide formation and sacrificial oxide growth. However, conventional thermal processing of the semiconductor device subsequent to the formation of the implant regions has the effect of facilitating the diffusion of the field implant region downwardly and laterally inward. The lateral inward diffusion is undesirable as it adversely impacts the concentration of other types of materials which form the source and drain regions for the field effect transistors. The resulting lateral diffusion further results in dopant diffusion into active channel regions therefore affecting the body effects (of narrow width devices), threshold voltage instability, and higher junction leakage.
The formation of buried contact diffusion regions for use with thin film transistors have problems similar to that discussed above, that is, with buried contacts, the out diffusion of ions into the field oxide region degrades its isolation characteristics. In particular, the prior art practice, particularly in the fabrication of SRAM devices normally provides such buried contact regions into the bulk substrate prior to the provision of the thin film transistor layer. As will be recognized, subsequent thermal processing of the semiconductor wafer has the effect of diffusing the buried contact region downwardly and laterally inwardly thereby producing deleterious results. Still further, bulk well formation is normally provided after the deposit of a gate oxide and conductive gate layer. Subsequent thermal processing of the semiconductor device also results in the diffusion of the bulk well.
It would be desirable to improve upon the methods of forming diffusion type regions and bulk wells for devices such as thin film transistors, SRAMS, DRAMS, resistors in SRAMS, and similar assemblies. Such is the subject matter of the present invention.